Đề xuất hàm offset giảm tổn hao do sự chuyển mạch cho nghịch lưu cầu H-NPC 5 bậc

Nội dung text: Đề xuất hàm offset giảm tổn hao do sự chuyển mạch cho nghịch lưu cầu H-NPC 5 bậc

1. ĐỀ XUẤT HÀM OFFSET GIẢM TỔN HAO DO SỰ CHUYỂN MẠCH CHO NGHỊCH LƯU CẦU H-NPC 5 BẬC A NOVEL OFFSET FUNCTIONS DESIGN FOR FIVE-LEVEL H-BRIDGE NPC INVERTERS TO REDUCE SWITCHING LOSS Quach Thanh Hai1 Do Duc Tri1 Phan Thanh Minh1 Danh Tuan Le2 Duong Tran Dinh Thao2 1Advanced Power Electronics Lab, D405, Ho Chi Minh city University of Technology and Education 2Kien Giang Colleges of Economic and Technical TÓM TẮT Bài báo này trình bày kỹ thuật điều chế sóng mang thông qua việc sử dụng hàm offset nhằm giảm tổn hao do sự chuyển mạch của các khóa công suất cho nghịch lưu cầu H-NPC 5 bậc. Kỹ thuật này sử dụng hàm offset là thành phần bậc 3 để chuyển các sóng điện áp điều khiển về ngưỡng cực đại hoặc cực tiểu của biên độ các sóng mang tại thời điểm dòng điện pha không đạt cực tiểu và biên độ dịch chuyển của điện áp điều khiển là cực tiểu. Khi điện áp điều khiển về ngưỡng cực đại hoặc cực tiểu của biên độ các sóng mang sẽ giảm giao cắt giữa sóng điều khiển và sóng mang để giảm số lần chuyển mạch ở vùng tổn hao do sự chuyển mạch lớn. Với kỹ thuật xây dựng hàm offset trình bày trong nghiên cứu, các khóa công suất đang chịu dòng tải lớn sẽ hạn chế chuyển trạng thái. Do đó tổng tổn hao do sự chuyển mạch sẽ giảm. Kết quả của giải thuật được kiểm chứng qua mô phỏng. Từ khóa: Điều chế sóng mang, hàm offset, giảm số lần chuyển mạch, nghịch lưu, 5 bậc. ABSTRACT This paper presents a new carrier pulse width modulator algorithm to reduce switching loss in five-level H-bridge neutral point clamped inverter. The proposed technique is based on the offset function being 3rd harmonic voltage. The offset voltage will be added to the control voltages so that the voltage of phase which has absolute of load current largest move into top (or bottom) of the carriers. So reducing the intersection of control voltage in that phase and the carriers and then reducing the number of switching losses. With the pulse width modulation method and flexible offset voltages in this study, switching loss in a cycle will be decrease. Simulation results will be provides in order to validate the proposed algorithm. Keywords: Carrier based pulse width modulation, offset function, reducing the number of switching losses, five-level H-bridge neutral point clamped inverter, control voltage. 1. INTRODUCTION to electrical grids. Space-vector pulse width Multilevel inverters are power electronic modulation and carrier based pulse width converters that play important roles in modulation are the typycal control applications of mechanical-electrical techniques of inverters [10]. Because of systems, transfortation, power quality industrial requirements, the inverters made management, renewable energy conversion with the capacity greater than [1]. Due to the such as solar energy, wind energy connected increase in capacity of the inverters, the
2. power loss becomes a problem that needed to load current) on the top or bottom level of solve. the carrier. Because the duration of each It causes power losses in inverter phase, reaching its absolute of load current including loss in power source (PS), loss in on maximum, are the same and equal 1/3 wires (Pl), loss in control circuit (PDr), and cycle of control voltage, the number of loss in switches (PSW) [5]. Of the power switching will decreased about 33 percent. losses mentioned above, loss in switches is Proposed algorithm will be simulated on the largest, depending on modulation five-level H-bridge NPC topology in algorithm and topology [7]. The loss on Mathlab and PSIM software. switches of the inverter on a period of control voltage can be determined as (1): 2. TOPOLOGY OF FIVE-LEVEL BRIDGE H-NPC INVERTERS PPP SW SS CS (1) Where PCS and PSS are conductive and Sa11 Sa13 switching loss of switches. 푃 = ∑ 푃 (2) Sa12 Sa14 푆푆 푆,푖 Vc1 + 푖=1 th - PS,i is switching loss on the i switch; p are + a number of switches in topology. - th According to [11], the switching loss on the i Vc2 + Sa21 Sa23 switch (PS,i) depends on the number of - switching in a control voltage cycle and is determined by the formula (3). Sa22 Sa24 퐧 퐦 퐏퐒,퐢 = ∑ 퐄퐎퐍 . 퐕퐂퐄퐢. 퐈퐂퐢 + ∑ 퐄퐎퐅퐅 . 퐕퐂퐄퐣. 퐈퐂퐣 (3) 퐢= 퐣= n Where n is the number times of status changed from OFF to ON; m is the same Figure 1. A phase of five-level H-bridge NPC from ON to OFF. EON and EOFF are the inverter. energies for switching ON and OFF, Structure of a phase of five level H-bridge respectively. VCEi and ICi are the voltage NPC inverter is in figure 1 [3]. Hence, the across power switch before conducting and voltage from phase to pole (Uxgj) is the current after conducting at ON state i, determined by(4): respectively; VCEj and ICj are the voltage Uxgj = (TSxj).Uxj = (TSxTj - TSxPj).Uxj (4) across power switch after being OFF and the current before being OFF conducting at OFF Where TSxch is defined in (5) with Ch=T, P state j, respectively. (showed by left side branch and right side branch, respectively). Because VCEi, VCEj and supply voltage are equal, so that, reducing the switching or TSxj = TSxPj - TSxTj (5) the switching takes place at a smaller of IC, it Where j is the index of switches (1 to 4) will reduce switching losses. There are base and T is the state of switch. of the algorithm to reduce witching loss. The So, the phase to pole voltages is given study [11] shows reducing switching by (6): frequency often has the side effect is U ag TSaT TSaP increased THD, so content paper proposes a U u T T new modulation technique reduces the bg dc SbT SbP (6) number times of the switching on the phase U cg TScT TScP that absolute of load current value is The phase voltages and line to line voltages maximum. The proposed algorithm based on of five-level H-bridge NPC inverter is given the use of the offset function put voltage by (7) and (8): control (which has maximum of absolution
3. necessary for the proposed algorithm to U an 2 1 1 U ag 1 reduce switching in the phase which load U bn 1 2 1 U bg (7) 3 current (IC) none smallest. This is the ideal U cn 1 1 2 U cg solution to reduce energy losses due to switching without sacrificing THD as U an 2 1 1 TSaT TSaP udc prescribed. U bn 1 2 1 TSbT TSbP (8) 3 4. PROPOSED ALGORITHM U cn 1 1 2 TScT TScP 4.1.1. The principle of algorithm Thus, phase to pole voltages Uxg and line On 3-phase five-level H-bridge NPC inverter, to line voltages Uxy have the third order because the voltage across the switchVCEi harmonic while the phase voltage Uxn do not. and VCEj is always UDC / 2, so the switching Therefore, it can be seen that if offset loss depends on current through power function in the proposed algorithm of switches and the number of switching in the inverter control which is the third order period of control voltage [2]. Thereby harmonic will not affect the magnitude of the reducing the switching on the phase has third order harmonic of the load. Besides, the maximum (priority first-if can) or medium phase to pole voltage Uxg will have 5 level (priority second) of absolution load current. including two positive levels, two negative Define: vx is control voltage initial phase x, levels and zero. There are ±2U, ±U, and 0. vrx is calculated control voltage from 3. CARRIER PWM ALGORITHM TO algorithm. Select 0 is the bottom of the REDUCE THE NUMBER OF SWITCHING carrier with the smallest amplitude and peak This CPWM algorithm proposed in [12]. amplitude of the triangle carrier waves are The main idea in this algorithm is add a equal and equal to 1, then this time the third order harmonic, called offset voltage, threshold comparison of the carrier will be 0, to control signal, with the aim of reducing 1, 2, 3 and 4. The control voltage of phase x the switching of the leg phase has is vx is determined by (9). difference between the control voltages and 푣 = 푣1, cos(휔푡 + 푗 ) + 2 + 푣표 푠푒푡 (9) nearest carriers is the smallest. Call vx is Define Lx and εx as follows: voltage to control x phase, and vrx is 푖푛푡(푣 ) 푖 푖푛푡(푣 ) < 4 calculated control voltage from the PWM 퐿 = [ (10) 푖푛푡(푣 ) − 1 푒푙푠푒 modified algorithm to reduce switching 푒 = 푣 − 퐿 (11) frequency. The principle of this algorithm Call IxABS is the absolute value of current was showed in Fig 2 [12]. across phase x. And define the matrixes as (12 to 17) [ ] = [ , , ] (12) 1 푖 = max ( , , ) = { 푆 푆 푆 푆 0 푒푙푠푒 [ 푖푛] = [ 푖푛, 푖푛, 푖푛] (13) 1 푖 = min ( , , ) 푖푛 = { 푆 푆 푆 푆 0 푒푙푠푒 [ 푒 ] = [ 푒 , 푒 , 푒 ] (14) Figure 2. Principle of the CPWM algorithm 푒 = 1 − − 푖푛 to reduce number of switching [12] [ ] = [푒 , 푒 , 푒 ] (15) 1 푖 푒 = max (푒 , 푒 , 푒 ) 푒 = { The simulation results show that this 0 푒푙푠푒 [ 푖푛] = [푒 푖푛, 푒 푖푛, 푒 푖푛] (16) algorithm allows reducing the switching of 1 푖 푒 = min (푒 , 푒 , 푒 ) 푒 푖푛 = { the leg phase that different of control 0 푒푙푠푒 voltages of it with nearest carrier is smallest. [ 푒 ] = [푒 푒 , 푒 푒 , 푒 푒 ] (17) Therefore switching can do on the phase that 푒 푒 = 1 − 푒 − 푒 푖푛 has load current (absolute) being smallest. So switching loss is not minimums. Then it is
4. elements of the matrixes are only valid "0" and "1" so the calculation will be very fast and easy. 4.1.2. Flow chart From 4.1.1, the flow chart of proposed algorithm built as figure 5. The flow chart shows that the proposed algorithm uses Figure 3. Principle of the proposed algorithm simple commands as plus, minus, comparison of the program. So that with va, vb, and vc showed in fig 3a, there are four cases and then we can decide offset voltage as in table 1 Table 1 Case Conditions Fig Offset 1 amax=1; 3b 1-ea eamax=1 2 cmax=1; ecmin=1 3c -ec 3 bmax=1; 3b 1-ea ebmed=1; amed=1 4 bmax=1; 3c -ec ebmed=1; cmed=1 So general offset function is determined as (18). 푣표 푠푒푡 = −푒 푖푛. ([ ]. [푒 푖푛] + [ ]. [푒 푒 ] . [ 푒 ]. [푒 푖푛] ) (18) + (1 − 푒 ). ([ ]. [푒 ] + [ ]. [푒 푒 ] . [ 푒 ]. [푒 ] ) Control voltage (vrx) after added offset will move to the new location inside phase has minimum of offset and the absolute value of the load current being maximum or medium. (Figure 4) Figure 5. The proposed flow chart The comparison of the phase currents can be done by comparing circuits (hardware and does not require use of expensive sensors).Thus, calculation time is low, suitable for closed-loop control or other Figure 4: controlled Voltage initially and control methods. after applied the proposed algorithm m=0.7. 5. SIMULATIONAND EXPERIMENTAL Formula (18) may seem complicated, but the RESULTS.
5. The proposed algorithm will be proven phase voltage go respectively 6.03% and on model five level H-bridge NPC lower than the required under the present in inverter having a 100V DC voltage source, standards of Vietnam (TCVN-7909 the carrier frequency of 3000Hz, a 2.2-2008) and also meet the standards EMS three-phase load balance of R = 10Ω, L = according to international standards 30mH. EN6100-2-2 (Figure 6). Figure 6 are simulation results at modulator index m=0.7 and m=0.9. The simulation results show that when the absolute of phase current “A” reach maximum (some time medium) – T1, then switching on the phase is lower than it when phase current near zero (T2). Figure 7: Analyze the THD of phase voltage applied proposed algorithm index m = 0.9 Figure 8 is the comparison between the proposed algorithm and minimum common mode algorithm of Total Harmonic Distortion (THD) of phase voltage. Results in Figure 8 shows that Total Harmonic Distortion (THD) of phase voltage applied propose algorithm is greater than in applied (a) m = 0.7 minimum common mode algorithm at the same modulation index. However, with the modulation index m≥0.5 proposed algorithm get value total harmonic distortion is smaller than the standards of Viet Nam. 50 40 Min CM Proposed 30 20 10 0 (b) m = 0.9 0.05 0.25 0.45 0.65 0.85 Figure 6: The results of the simulation proposed algorithm. Figure 8: Relations modulation index and THD% phase voltage applied propose and The same things are happening when minimum common mode algorithms m=0.9. Therefore considering modified algorithm reduces the number of switching then this algorithm also reduces the switching similar and it is about 30%. So certainly, losses due to the switching will be smaller too. At modulation index m = 0.9, the total harmonic distortion (THD%) of
6. switching positions of the phase having maximum of absolute of phase current therefore proposed algorithm can reduce switching losses. This algorithm can not only reduce the number of switching, but also select phase having larger current for reduce of switching. With proposed algorithm, we only need to determine the phase that having the largest, smallest and average of the current phase. So Figure 9: Control characteristics that, we can use the logic circuits and no need to use ADC. These lead to reduced hardware The control characteristic of the proposed costs and increase computing speed. algorithm is nearly linear and similar to that of medium common mode algorithm REFERENCES (Figure 9). Control characteristic of proposed [1] Bin Wu, “High-Power Converters and algorithm and it of [14] are the same. Figure 10 shows a comparison of the number of ac Drives”, IEEE Press/Wiley, November times switching per cycle control voltage 2005, ISBN: 0-4717-3171-4. applied propose algorithm and minimum common mode algorithm with carrier [2] Bui Van Hieu, “Studies 3-phase frequency is 3 kHz. five-level H-bridge NPC power supply”, 70 Master thesis, Ho Chi Minh City University 60 of Technology and Education, 2013. 50 [3] B. Wu, Z. Cheng, “A Novel Switching 40 30 Sequence Design for Five-Level H 20 NPC-Bridge Inverters With Improved Output 10 M Voltage Spectrum and Minimized Device P 0 Switching Frequency”, IEEE Transactions 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 on Power Electron 6 2007, pp. 2138–2145. Figure 10: The number of times switching in period of control voltage applied proposed [4] C. A. dos Santos and F. L. M. Antunes, and minimum common mode algorithms. “Losses Comparison Among Carrier-Based The number of switching on the proposed PWM Modulation Strategies in Three-Level algorithm is lower than that of medium common mode algorithm by 33.33% Neutral-Point-Clamped Inverter”, corresponding decrease 1/3 switching International Conference on Renewable frequency and it same when applied the algorithm [11]. Energies and Power Quality, Spain 6. CONCLUSIONS April-2011. The paper presents the carrier based pulse [5] Di Zhao, Narayanan and Raja Ayyanar, width modulation algorithm by using offset “Switching Loss Characteristics of function to reduce the number of commutations of power switches in bridge Sequences Involving Active State Division H-NPC five-level inverters special reduced in Space Vector Based PWM”, Applied
7. Power Electronics Conference and multi-level inverter”, PhD thesis, Ho Chi Exposition, APEC '04, Vol 1, 2004. Minh city University of encyclopedia, [6] Le Van Manh Giau, “Balancing neutral 2013. point voltage three-level H-bridge NPC [11] Quach Thanh Hai, Trần Thu Hà, Danh inverter using zero - sequence voltage zero – Tuan Le, “Carrier modulation algorithm sequence voltage”, Master thesis, Ho Chi reduces switching frequency for five level Minh city University of Technology and H- bridge NPC inverter”, Journal of Education, 2013. Engineering Education ISSN 1859 1272, Vol [7] M. H. Bierhoff, F. W. Fuchs, 34 November 2015, pp 36-41. “Semiconductor Losses in Voltage Source [12] Quach Thanh Hai, Do Duc Tri, Bui and Current Source IGBT Converters Based Minh An, “Carrier PWM technique to reduce on Analytical Derivation”. switching for 5 levels H-brigde NPC [8] Nguyen Van Nho, Doi Van Mon, Tran inverter”, Journal of Engineering Education Quoc Hoan, Quach Thanh Hai “PWM ISSN 1859 1272, Vol 37 September 2016, pp modulation techniques to balance voltage 7-14. two capacitor DC in three-level NPC [13] Vo Xuan Nam, “Balanced DC-Link inverter”, National Conference 6th voltage for multi-level NPC inverter”, mechatronics - VCM – 2012. Master thesis, Ho Chi Minh city University [9] N. V. Nho, M. J. Youn, “A of Technology and Education, 2012. Comprehensive Study On SVPWM – Carrier [14] Wei Wu, Jianguo Jiang, Guifeng Wang, Based PWM Correlation In Multilevel Shutong Qiao, He Liu, “A Multilevel Inverters”, IEE Proceedings -Electric Power SVPWM Algorithm for Linear Modulation Applications, 2005. and Over Modulation Operation”, Sensors & [10] Quach Thanh Hai, “Studies technical Transducers, Vol. 159, Issue 11, November pulse width modulation controller optimized 2013, pp. 198-205. Contact information: Quach Thanh Hai, PhD. Advanced Power Electronics Lab, D405, Ho Chi Minh city University of Technology and Education Tel: 0903.688.130, Email: haiqt@hcmute.edu.vn
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