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Bài giảng Vi xử lý - Chương 3: Họ vi điều khiển 8051

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Nội dung text: Bài giảng Vi xử lý - Chương 3: Họ vi điều khiển 8051

  2. ươa
  4. Memory 0 Address Bus Program CPU Data Bus + Data Von Neumann 2n Architecture Memory 0 Address Bus Program CPU Fetch Bus Harvard Address Bus 0 Architecture Data Bus Data
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  11. O • Khả năng lái là 4 tải TTL loại LS (Low Power Schottky) với các cổng P1, P2, và P3; và 8 tải TTL loại LS với cổng P0. • Chú ý là điện trở kéo lên bên trong không có trong Port 0 (ngoại trừ lúc làm việc như bus dữ liệu / địa chỉ bên ngoài). Điện trở kéo lên có thể được sử dụng với P0 tùy theo đặc tính vào của thiết bị mà nó lái.
  12. A Pin of Port 1 Read latch Vcc TB2 Load(L1) Internal CPU D Q P1.X bus P1.X pin Write to latch Clk Q M1 TB1 Read pin ⌦P0.x 8051 IC
  13. Writing “1” to Output Pin P1.X Read latch Vcc TB2 Load(L1) 2. output pin is 1. write a 1 to the pin Vcc 1 Internal CPU D Q P1.X bus P1.X pin 0 output 1 Write to latch Clk Q M1 TB1 Read pin 8051 IC
  14. Writing “0” to Output Pin P1.X Read latch Vcc TB2 Load(L1) 2. output pin is 1. write a 0 to the pin ground 0 Internal CPU D Q P1.X bus P1.X pin 1 output 0 Write to latch Clk Q M1 TB1 Read pin 8051 IC
  15. Reading “High” at Input Pin Read latch Vcc 2. MOV A,P1 TB2 external pin=High 1. write a 1 to the pin MOV Load(L1) P1,#0FFH 1 1 Internal CPU bus D Q P1.X pin P1.X 0 Write to latch Clk Q M1 TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC
  16. Reading “Low” at Input Pin Read latch Vcc 2. MOV A,P1 TB2 1. write a 1 to the pin Load(L1) external pin=Low MOV P1,#0FFH 1 0 Internal CPU bus D Q P1.X pin P1.X 0 Write to latch Clk Q M1 TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC
  17. Other Pins • P1, P2, and P3 have internal pull-up resisters. – P1, P2, and P3 are not open drain. • P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. – P0 is open drain. – Compare the figures of P1.X and P0.X.  • However, for a programmer, it is the same to program P0, P1, P2 and P3. • All the ports upon RESET are configured as output.
  18. A Pin of Port 0 Read latch TB2 Internal CPU D Q P0.X bus P1.X pin Write to latch Clk Q M1 TB1 Read pin ⌦P1.x 8051 IC
  19. Port 0 with Pull-Up Resistors Vcc 10 K P0.0 Port DS5000 P0.1 P0.2 8751 P0.3 P0.4 0 8951 P0.5 P0.6 P0.7
  20. Port 3 Alternate Functions P3 Bit Function Pin P3.0 RxD 10 P3.1 TxD 11 P3.2 INT0 12 P3.3 INT1 13 P3.4 T0 14 P3.5 T1 15 P3.6 WR 16 P3.7 RD 17 ⌦
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  43. eeaoaeaa aeeaeoe eaeoaaa eeeeaa eaa eeeaa eeaa eaeae oeae oae
  44. o oa
  45. eoe eaeoe eaa ae mov A, #0 ;put 0 in the accumulator ;A = 00000000 mov R4, #11h ;put 11hex in the R4 register ;R4 = 00010001 mov B, #11 ;put 11 decimal in b register ;B = 00001011 mov DPTR,#7521h ;put 7521 hex in DPTR ;DPTR = 0111010100100001
  46. eoe eaeoe oe MOV DPTR,#7521h MOV DPL,#21H MOV DPH, #75 COUNT EQU 30 ~ ~ mov R4, #COUNT MOV DPTR,#MYDATA ~ ~ 0RG 200H MYDATA:DB “HELLO”
  47. oo “” eoeaeaeaa eoeoeaaeeae “h” aeaaee “b” aea aeeoeeae base-10 e ‘ ’ oeoeaaae eeea base-16 eae a “0” MOV A,#ABh MOV A,#0ABH
  48. ooa eaeae oe eae aa aa machine code= 243d eae oe eae o machine code= ABE8
  49. eoe eoe ae ae MOV A,4 ≡≡≡ MOV A,R4 MOV A,7 ≡≡≡ MOV A,R7 MOV 7,6 ≡≡≡ MOV R7,R6 MOV R2,#5 ;Put 5 in R2 MOV R2,5 ;Put content of RAM at 5 in R2
  50. Addressing Modes eoe eaaae aoo Mov a, 70h ; copy contents of RAM at 70h to a Mov R0,40h ; copy contents of RAM at 40h to a Mov 56h,a ; put contents of a at 56h Mov 0D0h,a ; put contents of a into PSW
  51. Eo o Oo MOV 80h, A or Copy contents of register A to location 80h MOV P0, A (Port 0 latch) MOV A, 80h or Copy contents of location 80h (Port 0 pins) to MOV A, P0 register A MOVABC A,EQU ABC 80h Copy; equate contents from direct address with label MOV A, ABC ABC; Port 0 to to register A A MOV R0, 12h Copy contents from RAM location 12h to register R0 MOV 0A8h, 77h or Copy contents from RAM location 77h to IE MOV IE, 77h register of SFRs MOV direct,direct oeoeo
  52. Eo ooaoo ooaoo ooaooo e “ ” a MOV DIRECT, DIRECT
  53. o O o oo oo PUSH direct POP direct a a a a a a
  54. E Show the code to push R5, R6, and A onto the stack and then pop them back into R2, R3, and B, where register B = register A, R2 = R6, and R3 = R5. ooa ooa eeooa oooaoee oeeee oooao o oooao o
  55. oo eaeaeeooee – ea ooeaa oo aeao eaee o Eg. MOV A, A aa o aoaeeoa aa o oeaaoo
  56. eoe eee eeoeo eaooeo ee MOV R0,A MOV A,R7 ADD A,R4 ADD A,R7 MOV DPTR,#25F5H MOV R5,DPL MOV R1,DPH Note that MOV R4,R7 is incorrect
  57. ooa eeae oe 070D E8 mov a,r0 ;E8 = 1110 1 000 070E E9 mov a,r1 ;E9 = 1110 1 001 070F EA mov a,r2 ;EA = 1110 1 010 0710 ED mov a,r5 ;ED = 1110 1 101 0711 EF mov a,r7 ;Ef = 1110 1 111 0712 2F add a,r7 0713 F8 mov r0,a 0714 F9 mov r1,a 0715 FA mov r2,a 0716 FD mov r5,a 0717 FD mov r5,a
  58. oo oo oeeooeoae oaeoe eeeeeeeeae eaoeaaeee Acc a Rn ooeeoaaeee Rn eeoaoe e ;Use the following : MOV A, R7 MOV R4,A MOV R4,07H ; this is direct addressing mode
  59. o aeoaeoaoooeae eaeoe oeoooaao eooa O eoaeaeeaao aeeoeaeoa eoaoeaoaaaeo eaeoa
  60. eoe eee eaeoeoeo eaoeeee eeeoo ae mov psw, #0 ; use register bank 0 mov r0, #3Ch mov @r0, #3 ; M[3Ch]  3 eeeo aee mov dptr, #9000h ; dptr  9000h movx a, @dptr ; a  M[9000h] oe aaaeeeaeo
  61. 8051 Instruction Format eeeae oe oao 070D E7 mov a,@r1 070D 93 movc a,@a+dptr 070E 83 movc a,@a+pc 070F E0 movx a,@dptr 0710 F0 movx @dptr,a 0711 F2 movx @r0,a 0712 E3 movx a,@r1
  62. eeeeoaee o
  63. eaeeooeaeoeoeae aeeaa pointer Only R0 and R1 aeeeaaee aeaeo – e R0 ,R1 a DPTR aeeeaee ea eooaoe a “@” eoeeeeae
  64. Program memory ACC ACC Addresses 10 ⊕⊕⊕ 22 200 ADD A, @R0 R0 R0 201 31 31 Data memory 30 31 12 Before After 32 8051 Internal data memory
  65. Eo o Oo MOV @R1, A Copy the data in A to the address pointed to by the contents of R1 MOV A, @R0 Copy the contents of the address pointed to by register R0 to the A register MOV @R1, #35h Copy the number 35h to the address poi nted to by register R1 MOV @Ri,#data where i = 0 or 1 MOV @R0, 80h or Copy the contents of the port 0 pins to the MOV @R0, P0 address pointed to by register R0. MOVX A, @R0 Copy the contents of the external data address pointed to by register R0 to the A register MOVX A, @DPTR Copy the contents of the external data address pointed to by register DPTR to the A register
  66. E eaoaeeooe aeoeooao o a eaeoe eeeaeoe oaooa aoo
  67. oooE Direct addressing mode oaae oooao oooao oooao oooao oooao
  68. oooE register indirect addressing mode without a loop oaae oaeoe oooaooo eeoeo oooaooo eeoeo oooaooo eeoeo oooaooo eeoeo oooaooo
  69. oooE Loop method oaoea oaoe oooaooo eeoe oooeeo MOV R2, #05h ; example “DJNZ” : decrement and jump if Not Zero LP: ; ; do 5 times inside the loop DJNZ direct, relative ; DJNZ Rn, relative where n = 0,1,,,7 DJNZ R2, LP ; R2 as counter
  70. Eoo eaoaeeoea oaoaaae oaoe oaoe eaoaooo eeoe oooeeo ; clear one ram location at address 60h CLR A MOV R1,#60h MOV @R1,A Setup a loop using DJNZ and register R7 as counter
  71. Eo eaoaeeooaooeo aaooaoaao oaoaa oeoe eaooe oe eaeooe ooeao eeoeoe eeeaooe eeooaee
  72. oo oeeoaeaea dynamic data structures aaaae aaaeaaaeoe oeeaeeeaaooe aeoaaaeeeaooeao oeooaoaeaoaee Register or direct addressing (eg. MOV A, 30H ) cannot be used , since they require operand addresses to be known at assemble-time.
  73. eoe eeeeoe oeo eaoaeeoeae ae aeaaoe aeaeae o mov dptr, #4000h mov a, #5 movc a, @a + dptr ;a  M[4005]
  74. eoe eeeeoe oe aeaeaeo ORG 1000h 1000 mov a, #5 PC 1002 movc a, @a + PC ;a  M[1008] 1003 Nop ooae o aea ea oeeo
  75. MOVC A, @A+ DPTR MOVC A, @A+ PC JMP @A+ DPTR a base register aoaa offset ooaeooo eeeeaeoa o o eoaeoaaaoeoa ooae ae eaeeeae “” eoe eaeeeaeoaeoe
  76. Example: MOVC A,@A+DPTR Program memory ACC ACC 00 10 ⊕⊕⊕ 56 DPTR 41 56 31 Before After 2000 MOVC A, @A + DPTR 2001
  77. Eo o Oo MOVC A, @A + DPTR Copy the code byte, found at the ROM address formed by adding register A and the DPTR register, to A MOVC A, @A + PC Copy the code byte, found at the ROM address formed by adding A and the PC, to A JMP @A + DPTR Jump to the address formed by adding A to the DPTR, this is an unconditional jump and will always be done.
  78. EooEoo eaoaoee x aeoa e x2 ooo oaooaeae oeao e eaeoae eo eeo
  79. o eoe aeoe aaeaeoeeoa aaeaeoeeoa aaeaeoee eeaeaoeoeeoee eaeoeeaao
  80. eoao eeaeaee e a ee oe oa ae o ee oe 0703 E500 mov a,00h 0705 8500E0 mov acc,00h 0708 8500E0 mov 0e0h,00h oo 070B E9 mov a,r1 070C 89E0 mov acc,r1 070E 89E0 mov 0e0h,r1
  81. eo aaeoe ee 0703 8500 F0 mov b,00h 0706 8500F0 mov 0 f0 h,00h 0709 8CF0 mov b,r4 070B 8CF0 mov 0f0h,r4 aeeae 0704 F580 mov p0,a 0706 F580 mov 80h,a 0708 859080 mov p0,p1 ooeoo
  82. e a aeaeeaeae ae ooe eoeaeae
  83. 8051 Instruction Format eaeae oe eaeae eeee machine code= 80FE (FE=-2) Range = (-128 ~ 127) oeae eeeo 07FEh oe 0700 1 org 0700h 0700 E106 2 ajmp next ;next= 706h 0702 00 3 nop 0703 00 4 nop 0704 00 5 nop 0705 00 6 nop 7 next: 8 end
  84. ooeaươ
  85. SJMP relative DJNZ direct, relative DJNZ Rn, relative, where n=0,1,,,7 e “ ”o eaeaeaae o Yoaeaeaeaeaa oe aeaeeeaoe eeoo eeoeeaeae eae
  86. eeaeaeaeoe eeaeoe e o oeeee aeoa oeee eaaeaooo eaeoeoe aeaeeeaoe eeoo
  87. Program Counter Branch Opcode Offset Next Opcode + Offset Program counter + offset = Effective address Next Instruction = address of next instruction
  88. Eo o Oo SJMP NXT Jump to relative address with the label 'NXT'; this is an unconditional jump and is always taken. DJNZ R1, DWN Decrement register R1 by 1 and jump to the relative address specified by the label 'DWN' if the result of R1 is not zero. 0035
  89. o ACALL address11 AJMP address11 eeo ACALL a AJMP aoeeaeoe eae “ ” aaeae 211 = 2048=2K The subroutine called must therefore start within the same 2K Block of the program memory as the first byte of the instruction following ACALL.
  90. o ACALL address11 ORG 00H ; reset location AJMP address11 LJMP START ; 3 bytes instruction ORG 3FFEH START: ACALL FORWARD ; 2 bytes instruction ; now code address at 4000H LJMP TEST ORG 47FFH ; 01000 1111111111B FORWARD: RET ORG 5800H ; 01011 00000000000B BACKWARD: RET ORG 5FFDH TEST: ACALL BACKWARD ; 2 bytes instruction ; now code address at 5FFFH SJMP $ END
  91. ooa oaeae oe • Range = (0000h ~ FFFFh) 0700 1 org 0700h 0700 020707 2 ajmp next ;next= 0707h 0703 00 3 nop 0704 00 4 nop 0705 00 5 nop 0706 00 6 nop 7 next: 8 end
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