Bài giảng Thiết kế logic số (VLSI design) - Chương IV: Thiết kế mạch số trên FPGA (Phần 3)

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1. Thiết kế logic số (VLSI design) Bộ môn KT Xung, số, VXL 06/2010
2. Quy trình thiết kế trên FPGA ISE (Intergrated Software Enviroment)
3. Quy trình thiết kế trên FPGA Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able Specification (Lab Experiments) to perform an encryption algorithm by itself, executing 32 rounds VHDL description (Your Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; Functional simulation entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Synthesis Post-synthesis simulation
4. Quy trình thiết kế trên FPGA Implementation Timing simulation Configuration On chip testing
5. VHDL and Schematic library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity compare_module is Port (value : in std_logic_vector (3 downto 0); res : out std_logic); end compare_module; architecture Behavioral of compare_module is signal std : std_logic_vector (4 downto 0); begin val <= '0' & value; process (val, std) begin sub <= val - std; res <= sub(4); end process; end Behavioral; Technology independent, HDL Easy to handle complex design Easy for Testing
6. Synthesis Synthesis Generate nelist (post Create RTL Check syntax Create Technology simulation schematic & synthesis schematic (optional) model) (optional) (optional)
7. Synthesis UNISIM Library library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity compare_module is Port (value : in std_logic_vector (3 downto 0); res : out std_logic); end compare_module; architecture Behavioral of compare_module is signal std : std_logic_vector (4 downto 0); begin val <= '0' & value; process (val, std) begin sub <= val - std; res <= sub(4); end process; end Behavioral;
8. Synthesis - netlist library IEEE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; use UNISIM.VPKG.ALL; entity sp3_led is port ( LED1 : out STD_LOGIC; LED2 : out STD_LOGIC; ); end sp3_led; architecture Structure of sp3_led is signal SW8_IBUF_31 : STD_LOGIC; begin LED81 : LUT2 generic map( INIT => X"1" ) port map ( I0 => SW8_IBUF_31, I1 => SW7_IBUF_29, O => LED8_OBUF_15 );
9. Synthesis – Technology Schematic
10. Synthesis – RTL Schematic
11. Synthesis – UCF file # IO location defination NET "HIGH_voltage" LOC = P102; NET "LOW_voltage" LOC = P100; NET "voltage[0]" LOC = P160; NET "voltage[1]" LOC = P161; NET "voltage[2]" LOC = P162; NET "voltage[3]" LOC = P163; # Timing constraint INST "LOW_voltage" TNM = "OUT_REG"; INST "HIGH_voltage" TNM = "OUT_REG"; NET "voltage[0]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING; NET "voltage[1]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING; NET "voltage[2]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING; NET "voltage[3]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING;
12. Implementation Translate Post-translate simulation model Post-map simulation model Mapping Implementation Post-map static Timing Post-place-route static timing Place & Route Post-place-route simulation model
13. Translate Synthesis Circuit netlist Timing Constraints Constraint Editor Electronic Design Native Interchange Format Constraint File EDIF NCF UCF User Constraint File Translation NGD Native Generic Database file
14. Mapping
15. Chương III FPGA Place & Route
16. FPGA Verification Verification On-circut Function Timing testing
17. Giao thức truyền tin nối tiếp IDLE START DATA PARITY STOP IDLE RX Tbraud Bit counter x 0 0 1 2 3 4 5 6 7 8 0 SAMPLE ONE BIT RECEIVING RX Sample counter 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
18. Máy trạng thái khối UART IDLE CNT16 = 8 and RX = 1 CNT_BIT = 8 RX = 0, Rx_Reg = 1 START FRAME RECEIVE DETECTOR DATA CNT16 = 8 and RX = 0
19. Sơ đồ khối UART SAMPLE COUNTER BIT COUNTER CLK CLOCK DIVIDER CLK16 CNT CNT RESET RESET ENABLE ENABLE nRESET FSM (FINITE STATE MACHINE) RX_REG RX_REG Rx RECEIVE_REG SHIFT_ENABLE DATA REG LOAD LEDs
20. Khối giao tiếp VGA
21. Tín hiệu quét VGA
22. Sơ đồ khối VGA HS DCM_CLK HORIZONTAL COUNTER CLK_IN DCM_BLOCK (optional) VS VERTICAL COUNTER vcount hcount R CHARACTER_ ROM G (optional) RGB GENERATOR B DATA_RAM (optional)