Bài giảng Kỹ thuật vi xử lý (Microprocessors) - Chương 6: Truy cập bộ nhớ trực tiếp DMA

Nội dung text: Bài giảng Kỹ thuật vi xử lý (Microprocessors) - Chương 6: Truy cập bộ nhớ trực tiếp DMA

1. © DHBK 2005 1/Chapter6 Nội dung môn học 1. Giới thiệu chung về hệ vi xử lý 2. Bộ vi xử lý Intel 8088/8086 3. Lập trình hợp ngữ cho 8086 4. Tổ chức vào ra dữ liệu 5. Ngắt và xử lý ngắt 6. Truy cập bộ nhớ trực tiếp DMA 7. Các bộ vi xử lý trên thực tế
2. © DHBK 2005 2/Chapter6 Chương 6: Truy cập bộ nhớ trực tiếp DMA • Giới thiệu về DMA • Mạch DMAC 8237A của Intel
3. © DHBK 2005 3/Chapter6 Giới thiệu về DMA
4. © DHBK 2005 4/Chapter6 Mạch DMAC 8237A của Intel
5. © DHBK 2005 5/Chapter6 Mạch DMAC 8237A của Intel • Although i8237A may not appear as a discrete component in recent PCs, it’s still there (integrated in chipsets, ISPC) • The i8237A has four independent DMA channels • Original PC/XT design had one i8237A for four DMA channels • PC/AT used two i8237As to provide 7 DMA channels • i8237A is programmable device and can be configured for single transfers, block transfers, Reads, Writes or Memory-to- Memory transfers
6. © DHBK 2005 6/Chapter6 Mạch DMAC 8237A của Intel • i8237A allows byte addressing for 8-bit data transfers • In the PC/AT design, a contrived 16-bit transfer design is implemented using the i8237A • i8237A uses a multiplexed address and data bus to reduce the device pin count. ❑ DB0 DB7 lines contain the data bus along with the high byte of the 16- bit address bus. ❑ An external latch is required to demultiplex the address lines
7. © DHBK 2005 7/Chapter6 Mạch DMAC 8237A của Intel
8. © DHBK 2005 8/Chapter6 Mạch DMAC 8237A của Intel
9. © DHBK 2005 9/Chapter6 Mạch DMAC 8237A của Intel
10. © DHBK 2005 10/Chapter6 How the PC uses the i8237A i8237A Address Latch and Page Registers I/O Mapped DMA A16 A23 to MPU, read Page [A16 A19 and write Regrs. for PC/XT] DMA A8 A15 Addr. Latch IOR DB0 DB7 IOW MEMR ADSTB MEMW i8237 DMA A0 A7 A0 A7 four HRQ DMA channels DREQ0 Hi DACK0 Q D HLDA DREQ1 15 usecs. DACK1 OUT1 DREQ2 CLR DACK2 8253 DREQ3 EOP DACK3 (8254) Timer/ Floppy Controller Counter
11. © DHBK 2005 11/Chapter6 DMA Address Tracking • The i8237A has four registers for tracking memory addresses during a DMA block ❑ BASE ADDRESS REGISTER ❑ BASE WORD COUNT REGISTER ❑ CURRENT ADDRESS REGISTER ❑ CURRENT WORD COUNT REGISTER
12. © DHBK 2005 12/Chapter6 DMA in the PC/XT
13. © DHBK 2005 13/Chapter6 DMA Cascadation Cascaded i8237As in the PC/AT Cascaded i8237A DMA Controllers DREQ0 DACK0 DREQ1 i8237A DACK1 Slave DREQ2 DACK2 DREQ4 DREQ3 DACK4 MPU HRQ DACK3 HOLDA DREQ5 i8237A DACK5 Master DREQ6 DACK6 DREQ7 DACK7
14. © DHBK 2005 14/Chapter6 PC/AT DMA Channel priorities • DMA channel 0 (DREQ0) has the highest priority • DMA channel 7 (DREQ7) has the lowest • Note, when a DMA transfer is in session, it cannot be 'interrupted' by another DMA request, even if the DMA request is made by a higher priority DMA channel. • The current DMA transfer session will be completed before the pending DMA request is accepted
15. © DHBK 2005 15/Chapter6 DMA Channels in the PC/AT DMA Priority Pre-defined 8-bit or Use in PC/AT 16-bit ___ DREQ0 Highest Memory Refresh* 8-bits DREQ1 Not defined 8-bits DREQ2 Floppy Disk 8-bits DREQ3 Not defined 8-bits DREQ4 Cascade not used DREQ5 Not defined 16-bits DREQ6 Not defined 16-bits DREQ7 Lowest Not defined 16-bits